1. Field of the Invention
The present invention relates to an information processing system and a logic LSI to which a master/checker method is applied, with the objective of improving the fault detection efficiency.
2. Description of Related Art
An information processing apparatus to which a master/checker method is applied, with the objective of improving the fault detection efficiency, already has been presented. For example, an information processing apparatus having the above-mentioned feature is disclosed in xe2x80x9cFault Tolerance Achieved in VLSIxe2x80x9d, by R. Emmerson et al., IEEE Micro., December 1984, pp 34-43.
In the above-mentioned apparatus, data output from a master unit is input to a checker unit via a data bus. The output data of the master unit input to the checker unit is compared with corresponding output data of the checker unit by a comparator provided in the checker unit. If a result of the comparison indicates a disagreement between both data, the comparator outputs a fault detecting signal, and the operation of the information processing apparatus is stopped.
On the other hand, due to recent rapid innovation in LSI processing techniques, a processor including many peripheral circuits, such as cache memory, has been developed. Therefore, it has been considered not sufficient for fault detection in an apparatus containing a plurality of processors, such as mentioned above, to be carried out merely by comparing a pair of data transmitted to a data bus.
As a method of improving the fault detection efficiency, it also has been proposed to execute a comparison between data output from one of the peripheral circuits integrated in a processor provided in a master unit and data output from a corresponding one of the peripheral circuits integrated in a processor provided with a checker, in addition to the comparison between data output on the data bus. However, if the fault detection is carried out for output data of all integrated circuits in a master unit and a checker, a new problem is caused, that is, a comparator for comparing data processed in the integrated circuits and the wiring among the integrated circuits and the comparators need a large area, respectively.
As a method of resolving the above-mentioned problem, xe2x80x9cA fault detection processing methodxe2x80x9d is disclosed in JP-A-129426/1985 by Hujiwara et al. In this method, the fault detection is realized by executing a comparison between a result of an exclusive OR calculation for data output from the integrated circuits of a processor in a master unit and a result of an exclusive OR calculation for data output from the integrated circuits of a processor in a checker. Although this method avoids the need to increase the area needed for a comparator and the wiring, faults of 2 bits cannot detected. Therefore, by this method, a sufficient fault detection efficiency can not be attained.
An objective of the present invention is to provide an information processing system and a logic LSI to which a master/checker method is applied, with the result of improving the fault detection efficiency, while suppressing the need to increase the amount of wiring (between pins of two LSIs in a system wherein a master unit and a checker are composed by using two different LSIs, or between a master unit and a checker in a system wherein a master unit and a checker are integrated in one LSI), and to increase the area needed for a comparator executing the comparison between a pair of corresponding data output from the master unit and the checker.
The first way to attain the above-mentioned objective is to provide an information processing system, including a plurality of information processing units, in which a fault occurring in the plurality of information processing units is detected by carrying out a comparison among data, each of the data being processed and output by each of the plurality of information processing units,
wherein each of the plurality of information processing units includes a processor circuit in which a plurality of internal circuits is integrated, an internal processing result outputting means for outputting respective result data processed by respective ones of the plurality of internal circuits, and an internal data selection circuit for selecting and outputting a selected one of the result data output from the internal processing result outputting means, at every predetermined timing, and
the information processing system further includes a comparator for executing a comparison among corresponding data, each of which is selected and output from the internal data selection circuit of each information processing unit, and for outputting a result of the comparison.
In this information processing system, it is preferable that buses are used for connection between the information processing units, and between the comparator and each of the information processing units, and at least one of the information processing units inputs data output from the internal data selection circuit provided in the unit itself to the comparator via the buses.
Further, in this information processing system, it is possible for the at least one of the information processing units, inputting data output from the internal data selection circuit provided in the unit to the comparator via the buses, to further include a first selector for selecting either the result data output from the processor circuit provided in the unit or data output from the internal data selection circuit provided in the unit.
The information processing system according to the present invention further includes a memory device, and data which is output from the above-mentioned processor unit to the memory device via the buses is also input to the comparator and compared with data which is output from the processor circuits of other information processing units and input to the comparator.
Further, in this information processing system, it is possible to include the comparator in one of the information processing units, and the information processing unit including the comparator further is provided with a second selector for selecting and outputting either data output from the processor circuit provided in the unit or data output from the internal data selection circuit provided in the unit, in synchronism with data selection by the first selector included in another information processing unit.
In the following, an example of operations of the information processing system according to the present invention will be explained.
The internal processing result outputting means of each processor circuit outputs result data processed by each of the internal circuits. The internal data selection circuit selects and outputs one of the result data output from the internal processing result data outputting means, at every predetermined timing (for example, an execution machine cycle of the processor circuit). The comparator executes a comparison between the data input from the internal data selection circuits provided in two of the information processing units, and outputs a result of the comparison. By monitoring the result of the comparison, it is possible to detect a fault occurring in the information processing system. That is, if the two compared data do not agree with each other, it means that some fault is occurring in the information processing system.
If the data output from the internal data selection circuit of each information processing unit is input to the comparator via the above-mentioned buses, it is not necessary to provide exclusive wires for inputting and outputting the data input to the comparator. Further, by selecting and outputting either the data output from the processor circuit or the data output from the internal data selection circuit to the buses, via the first selector, wires and terminals connected to the buses can be commonly used.
Moreover, if the comparison is carried out for data output from the processor circuit to the memory device by using the comparator, a fault occurrence can be also detected, based on the agreement between the corresponding data output from both processor circuits. In the case of providing the comparator in one of the information processing units, the second selector is controlled so as to select either the data output from the processor circuit or the data output from the internal signal selection circuit, in synchronism with the data selection of the first selector. Contents of a pair of data to be compared by the comparator are changed corresponding to the selection state of the first and second selectors (namely, the comparison between data output to the memory device from the processor circuit of the master unit and data output from the processor circuit of the checker unit including the comparator or the comparison between data output from the respective internal data selection circuits provided in the master unit and the checker unit).
A second way to attain the above-mentioned objective is to provide an information processing system including a plurality of information processing units, which detects a fault occurring in the plurality of information processing units by carrying out a comparison among data, each of the data being processed and output by each of the plurality of information processing units, the information processing system comprising a data transmission path for bidirectionally transmitting data among the information processing units,
wherein each of the plurality of information processing units includes a processor circuit in which a plurality of internal circuits are integrated, an internal processing results outputting means for outputting result data, processed by each of the plurality of internal circuits, to other information processing unit via the data transmission path, an internal data selection circuit for selecting and outputting one of the result data output from the internal processing results outputting means, at every predetermined timing, an internal data outputting means for outputting a part of the data output from the internal data selection circuit, and a comparator for executing a comparison between the part of the result data output from the internal data outputting means, which is output from the internal data selection circuit of the information processing unit, and a part of result data, corresponding to the part of the result data output from the internal data outputting means of another information processing unit, and outputting a result of the comparison.
Further, it is possible for each of the information processing units to include a simultaneous bidirectional interface for simultaneously inputting and outputting data via the data transmission path.
In the following, operations of the information processing system according to the present invention will be explained.
The internal processing result outputting means of each processor circuit outputs result data processed in each integrated circuit of the processor circuit. The internal data selection circuit selects and outputs one of the result data output by the internal processing result outputting means, at every predetermined timing (for example, the execution machine cycle of the processor circuit). The internal data outputting means outputs a part of the result data output from the internal data selection circuit via the data transmission path.
The comparator compares the part of the result data output from the internal data outputting means, which is output from the internal data selection circuit of the information processing unit, and a part of result data corresponding to the part of the result data output from the internal data selection circuit of another information processing unit via the data transmission path, and outputs a result of the comparison. By monitoring the result of the comparison, it is possible to detect a fault occurring in the information processing system. That is, if the two compared data do not agree with each other, it means that some fault is occurring in the information processing system. In this way, the plurality of information processing units share the fault detection. Therefore, if the disagreement in the comparison between a pair of the corresponding parts of the result data is detected by any of the information processing units, it is determined that some fault is occurring in the information processing system.
In this case, if inputting and outputting of the data output from the internal data outputting means are carried out by using a simultaneous bidirectional interface provided in each information processing unit, the number of pins for wiring among the units can be reduced. For example, if the internal data (the result data) selected by each internal data selection circuit is mutually transmitted between the units by a half of a data width of the internal data, the number of the pins can be reduced to xc2xd of the number necessary for transmitting the data of a full width.
For the above-mentioned first and second aspects of the present invention, it is preferable that the internal data selection circuit further outputs selection information for indicating which of the data output from the internal processing result outputting means has been selected, and the comparator outputs a result of the data comparison together with the selection information.
Moreover, it is possible for the information processing system to carry out recovery processing (a counter-measure) in response to the detected fault, corresponding to the contents of the result of the data comparison and the output selection information.
By carrying out the recovery processing, an optimal counter-measure can be performed for the system in which the fault is occurring, corresponding to the location of the fault occurrence.
A third way to attain the objective of the invention is to provide an information processing system including a plurality of processing nodes, wherein information processing is continued by switching from one processing node which is performing information processing when a fault is detected to another processing node, corresponding to the processing states of the information processing system, wherein each processing node includes a fault detection means for monitoring the state of processing of the node itself and for outputting information of a fault occurrence and a fault occurrence location if a fault is detected in the node, and the information processing system includes a switching means for switching from the processing node which is executing information processing to another processing node, after performing the predetermined counter-measure processing to the fault occurrence location.
Each of the processing nodes comprises a plurality of processor circuits, each of the processor circuits including a plurality of integrated internal circuits and an internal processing result outputting means for outputting result data processed by each of the internal circuits, and an internal data selection circuit which is connected to each of the processor circuits, for selecting and outputting one of the result data output from the internal processing result outputting means at every predetermined timing, wherein the fault detection means executes a comparison among the result data selected by the respective internal data selection circuits provided in the node, and outputs a result of the comparison together with the selection information for indicating which of data output from the internal processing result outputting means has been selected.
In the following, operations of this information processing system according to the present invention will be explained.
The fault detection means of the processing node monitors the states of the processing stages executed in the node itself, and outputs information of a fault occurrence and a fault occurrence location if a fault is detected in the node.
The above-mentioned fault detection is realized, for example, as follows. The internal processing result outputting means of each of the processor circuits provided in the processing node outputs the result data processed by each of the internal circuits provided in the processor circuit. Each of the internal data selection means basically selects and outputs different result data output from the internal processing result outputting means, at every predetermined timing. The fault detection means outputs a result of the comparison among the data selected by the internal data selection means in the node, as well as the selection information from each of the internal data selection means, the selection information indicating which of data output from the internal processing result outputting means has been selected.
The switching means of the information processing system switches from one processing node which is to execute the information processing to another processing node, after performing the predetermined counter-measure processing to the fault occurrence location.
In the above-mentioned first, second and third aspects of the invention, it is possible for each of the processor circuits to include a processing state outputting means for outputting states of processing executed in each of the internal circuits of the processor circuit, and the internal data selection circuit connected to the processor circuit changes data to be selected, corresponding to contents of the states of processing output from the processing state outputting means.
The processing state outputting means outputs states of processing executed in each internal circuit (for example, a state as to whether a cache memory integrated in each processor circuit is used or not). The internal data selection circuit changes data to be selected, for example, the internal data selection circuit removes data stored in the cache memory from candidates to be selected, if it is judged, by checking contents of data output from the processing state outputting means, that the cache memory is not to be used. By providing the processing state outputting means, since data processed in an internal circuit which does not execute significant processing is removed from the candidates to be selected by the internal data selection circuit and compared in the fault detection means, the fault detection can be more efficiently performed.
The fourth way to attain the objective of the present invention to provide a logic LSI comprises a processor circuit including a plurality of integrated internal circuits and an internal processing result outputting means for outputting result data processed by the internal circuits, and an internal data selection circuit for selecting and outputting one of the result data output from the internal processing result outputting means to the outside of the logic LSI, at every predetermined timing.
It is preferable that the above-mentioned logic LSI further includes a comparator for comparing the data output from the internal data selection circuit with data input from the outside of the logic LSI.
Further, it is possible for the logic LSI to include a simultaneous bidirectional interface for simultaneously inputting and outputting data by using a common signal wire, a part of the data output from the internal data selection circuit being output to the outside via the simultaneous bidirectional interface, and the data input from the outside is input via the simultaneous bidirectional interface.
It is preferable that the processor circuit further includes a processing state outputting means for outputting states of processing executed in each of the internal circuits of the processor circuit, and the internal data selection circuit connected to the processor circuit changes data to be selected, corresponding to the processing states output from the processing state outputting means.
In the following, operations of the logic LSI according to the present invention will be explained.
The internal processing result outputting means of the processor circuit outputs result data processed by each of the internal circuits. The internal data selection circuit selects and outputs one of the result data output from the internal processing result outputting means to the outside of the logic LSI, at every predetermined timing.
If a simultaneous bidirectional interface is used so that a part of the data output from the internal data selection circuit is output to the outside, and the data input from the outside (actual data output from the internal data selection circuit of other LSI) is received, the number of signal wires can be reduced.
In the logic LSI further including a comparator, the comparator compares the data output from the internal data selection circuit with the data input from the outside, and outputs a result of the comparison.
Moreover, in the logic LSI including a processing state outputting means, the processing state outputting means outputs processing states of each of the internal circuits (for example, a state as to whether a cache memory integrated in each processor circuit is used or not). The internal data selection circuit changes data to be selected, for example, the circuit removes data stored in the cache memory from candidates to be selected, if it is judged, by checking the contents of data output from the processing state outputting means, that the cache memory is not to be used. By providing the processing state outputting means, since data processed by an internal circuit which is not executing significant processing is removed from candidates to be selected by the internal data selection circuit and to be compared in the fault detection means, the fault detection can be more efficiently performed.